Browse NSN 5962-00-004-2130 Listing of Microcircuit Digita
It is our pleasure to inform you that part number 4-08764-007, SF110-18, 8-2130-37, SN8741F, 477-0580-001 listed under NSN 5962-00-004-2130 is now available and ready to ship from Fulfillment By ASAP. This part described as a Microcircuit Digita manufactured by Arma Div, Sylvania Electric Products Inc, Texas Instruments Incorporated, Boeing Company The, Freescale Semiconductor Inc. If you’d like a quick quote for NSN 5962-00-004-2130, please fill out the form from below. Are you looking to have it delivered today or tomorrow? We can help! Simply complete the Request For Quote (RFQ) form given below to get started, and we will get back to you within 15 minutes!
| Alternative NSN: 5962-00-004-2130 |
| Item Name: Microcircuit Digita |
| Federal Supply Class (FSC): 5962 Microcircuits Electronic |
| NIIN: 000042130 |
| NCB Code: USA (00) |
| Manufacturers: Arma Div , Boeing Company The , Freescale Semiconductor Inc , Inspektorat Wsparcia Sil Zbrojnych , Lansdale Semiconductor Inc , Motorola Ltd , On Semiconductor Corporation , Philco Ford Corp , Raytheon Company , Raytheon Technical Services Company , Sylvania Electric Products Inc , Texas Instruments Incorporated |
Characteristics Data of NSN 5962000042130
| MRC | Criteria | Characteristic |
|---|---|---|
| ADAQ | BODY LENGTH | 0.240 INCHES MINIMUM AND 0.275 INCHES MAXIMUM |
| ADAT | BODY WIDTH | 0.160 INCHES MINIMUM AND 0.185 INCHES MAXIMUM |
| ADAU | BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| AEHX | MAXIMUM POWER DISSIPATION RATING | 220.0 MILLIWATTS |
| AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| AFJQ | STORAGE TEMP RANGE | -65.0/+200.0 DEG CELSIUS |
| CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND NEGATIVE EDGE TRIGGERED AND W/ENABLE AND RESETTABLE |
| CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS |
| CQSZ | INCLOSURE CONFIGURATION | FLAT PACK |
| CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| CQZP | INPUT CIRCUIT PATTERN | DUAL 5 INPUT |
| CSSL | DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED |
| CTFT | CASE OUTLINE SOURCE AND DESIGNATOR | T0-85 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CWSG | TERMINAL SURFACE TREATMENT | GOLD |
| CZEN | VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -1.5 VOLTS MINIMUM POWER SOURCE AND 5.5 VOLTS MAXIMUM POWER SOURCE |
| CZEQ | TIME RATING PER CHACTERISTIC | 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| PMLC | PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| PRMT | PRECIOUS MATERIAL | GOLD |
| TEST | TEST DATA DOCUMENT | 99971-7531419 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAW |
| TTQY | TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
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